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The gate drive signals and timing diagram associated with the full bridge are shown in Figure 4. The power delivery interval of the phase shift topology is similar to the traditional full bridge converter, in that two diagonal switches are on (A&D or B&C). This applies the full input voltage across the. Mar 24, 2005 - designed for driving the MOSFETs in a full bridge configuration. Moment the gate drive voltage is equal to the voltage on pin VDD for the low.

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The PWD13F60 is a high density power driver integrating gate drivers and four N-channel power MOSFETs in dual half-bridge configuration. The integrated power MOSFETs have a low RDS(on) of 320 mΩ and 600 V drain-source breakdown voltage, while the embedded gate drivers high-side can be easily supplied by the integrated bootstrap diode. The high integration of the device allows loads in a tiny space to be driven efficiently. The PWD13F60 accepts a supply voltage (VCC) extending over a wide range and is protected by a low voltage UVLO detection on the supply voltage. The input pin extended range allows easy interfacing with microcontrollers, DSP units or Hall effect sensors.

The EVALPWD13F60 is 48 x 53 mm wide, FR-4 PCB resulting in an Rth(J-A) of 18 °C/W, capable to drive loads up to 2 ARMS, without forced airflow cooling. Both controlling and power signals are available on pin strip for easy connection to customer's board. Key Features • Power system-in-package integrating gate drivers and high-voltage power MOSFETs: Low RDS(on) = 320 mΩ, BVDSS = 600V • Suitable for operating as: Full-bridge or Dual independent half-bridges • Wide input supply voltage down to 6.5 VUVLO protection on supply voltage • 3.3 V to 15 V compatible inputs with hysteresis and pull-down • Interlocking function to prevent cross conduction • Internal bootstrap diodes.